A conventional technology is described hereinafter with reference to FIG. 12.
To start with, a structure according to a first example of the conventional technology is described. FIG. 12 is a circuit configuration diagram of a liquid crystal display using the conventional technology. Respective pixels of a display section 216 include a pixel switch 211 and a liquid crystal capacitor 212, and an opposite electrode of the liquid crystal capacitor 212 is connected to a common power supply line 217. The gate of the pixel switch 211 is connected to a vertical scanning circuit 215 via a gate line 214, and one end of the pixel switch 211 is connected to a DA conversion circuit 209 via a signal line 213.
An output of a latch circuit 208 is delivered to the digital/analogue (DA) conversion circuit 209 and an output of a sense amplifier 207 is delivered to the latch circuit 208. A signal from one end of a data line 203 is delivered to the sense amplifier 207. The data lines 203 are provided with the memory cells 221, respectively, the memory cells 221 being arranged in matrix fashion. As with memory cells of a DRAM (Dynamic Random Access Memory), the memory cells 221 each include one transistor switch and one capacitor (hereinafter referred to as “a 1T 1C configuration”), that is, a memory switch 201 and a memory capacitor 202, and the gate of the memory switch 201 is connected to a memory select circuit 205 via a memory gate line 204. The other end of the data line 203 is connected to a data input circuit 206.
Next, an operation of the first example of the conventional technology is described.
As a result of the memory select circuit 205 turning ON the memory switches 201 in a predetermined row via the memory gate line 204, memory data is read, and a signal thereof is amplified by the sense amplifier 207 to be subsequently written into the latch circuit 208. At this point in time, the memory select circuit 205 repeatedly reads the memory cells 221 corresponding to n-rows, thereby enabling the latch circuit 208 to read image data of n-bits.
The image data of n-bits as read is outputted from the latch circuit 208 to the DA conversion circuit 209, which converts the image data of n-bits into one analogue signal voltage to be then outputted to the signal line 213. At this point in time, the vertical scanning circuit 215 turns ON the pixel switch 211 at a predetermined address via the gate line 214, whereupon the analogue signal voltage is written into the liquid crystal capacitor 212 of the pixel as selected, thereby optically effecting image display.
In this connection, because the signal amplified by the sense amplifier 207 is written into the data line 203 as well, refresh operations of the memory cells are concurrently executed at this point in time.
With the conventional technology, image display can be effected without new input of image data from outside, so that low power consumption display can be effected with a peripheral drive circuit kept in a sleep condition.
Such an example of the conventional technology as described, is disclosed in detail in, for example, JP-A No. 085065/1999.
Further, with the example of the conventional technology, a memory cell layout is described again with reference to FIG. 13. FIG. 13 is a layout plan of the memory cells according to the first example.
One analogue image signal is stored by use of the memory cells 221 for n pieces (six pieces in FIG. 13), disposed in the column direction along each of the data lines 203. Accordingly, at the time of outputting data on one analogue image signal, corresponding to one word, it is necessary to output n pieces of data by scanning n lengths of the memory gate lines 204.
The memory cell layout according to the example of the conventional technology is disclosed in, for example, JP-A No. 085065/1999, and so forth, as described in the foregoing.
Meanwhile, another memory cell layout according to a second example of the conventional technology is described with reference to FIG. 14.
FIG. 14 is a layout plan of memory cells according to the second example of the conventional technology.
It represent the case where one analogue image signal is stored by use of the memory cells 221 for n pieces (six pieces in FIG. 14), disposed in the row direction along each of the memory gate lines 204. Accordingly, at the time of outputting data on one analogue image signal, corresponding to one word, it is necessary to obtain n pieces of data outputted to n lengths of the data lines 203.
The memory cell layout according to the example of the conventional technology, as described above, is disclosed in detail in, for example, JP-A No. 082656/2002, and so forth.